"PCI Latency" patch
for VIA Chipsets
README File
All executable and document files of this "PCI Latency" patch are Copyright (C) 2001-2003, George E. Breese. All Rights Reserved.
Version 0.20 BETA build 21
June 12 2003
Important notes:
Your computer's motherboard must contain a complete VIA chipset in order
for this patch to work. Check the model of chipset by
downloading and running CPUZ. If
the Mainboard section of CPUZ does not show a VIA chipset in the computer, then this patch will not work.
This product could, in a rare case, damage a computer. Use it carefully and at your own
risk. By using it, you agree to the license as shown below.
If you have installed a previous version of this driver, uninstall it
before installing this version.
Credits:
All credit for the original research on this patch is given to the site au-ja!
Their page review-kt133a-1.html
describes the problem and solution in German. Version 0.10 of this patch was
based entirely upon the recommendations of au-ja!.
I wish to thank the staff of Sudhian.com
(formerly VIAHardware.com)
for promoting my work. They have been supportive of my drivers since I first
began creating them. I also wish to thank WiNC, Franck, and all the testers who
helped refine and define the patch.
Thanks to Ryan of OCZTech.com for providing additional hardware for
testing.
Thanks to Sinjin for donating a sample of the Asus A7V133 motherboard for
testing. This motherboard was discontinued by Asus and was becoming hard to find
when I needed it to test a compatibility issue with version 0.19 of the patch.
License:
This software is licensed, not sold. The author of this product has
granted you a license to use this product, subject to the following conditions.
By possessing, using, or attempting to use this product, you assume all
liability for its use. You agree never to take legal action, civil or criminal,
against its author for any reason. You may redistribute this product in its
original form only. You may not charge money for distribution of the product,
unless all such charges are remitted to the author immediately upon payment. The
author retains ownership of all intellectual properties embodied in this
product.
About This Product:
This is a "patch" that can be applied to computers in order to solve problems
with the computer's PCI bus. This patch is designed for computers whose
chipset was made by VIA. You can discover
the maker of your computer's chipset by downloading and running
CPUZ from
www.cpuid.com , and examining the Mainboard
information.
This patch is commonly used to fix problems with sound cards, with USB
connections, or with IDE hard disks and DVD-ROM or CD-RW drives. But, it can be
used to help the performance of any PCI card in a VIA-based computer.
The changes made by this product are temporary. The computer's chipset erases
all changes automatically when being restarted, so the "patch" program must
reapply the changes each time Windows is started.
Installing the patch:
If you can read this file, the patch has been installed.
The patch is normally installed by downloading and opening VLATENCY_XXX.EXE,
where XXX is the version of the patch.
Uninstalling the patch:
In the "Add / Remove Programs" section of Control Panel, find the PCI Latency
Patch and press the button to remove it. If the computer is unstable, please
start Windows in Safe Mode before trying to uninstall the patch.
Files included:
VLATENCY.SYS - is the program file containing the patch for Windows
98, ME, NT 4.0,
2000, and XP. It is copied to WINDOWS\SYSTEM32\DRIVERS.
VLATENCY.INF - is the configuration file describing the installation
of the patch. It is copied to WINDOWS\INF.
PCI Latency Patch README.HTM - is this file. It contains warnings, quick instructions, and
last-minute information. It is copied to the Windows desktop.
Release Notes:
Version 0.20 beta 21
- Changed the Guaranteed CPU Time for the KT133/KT133A/KM133 to 2 CLKs. It
was set to zero previously.
- Enabled PCI Delay Transaction in the VT8235 southbridge, to smooth out
video capture cards when Athlon CPU cooling is enabled.
Version 0.20 beta 20
- Added registry settings: Rx00-RxFF, fl00-flFF, AGPRx00-AGPRxFF,
AGPfl00-AGPflFF, PCIDelayTransaction, HLTIdle, KT266AllowCMD1T, EnsoniqBoost,
PCIBusParking.
- The patch now checks the chip ID of the southbridge when choosing which
patches to apply to the northbridge. This allows the patch to take advantage
of the enhanced PCI performance of the VT8233A and VT8235 southbridge chips.
- Some of the KT133x patch has been reverted to (approximately) the 0.20b12
settings for testing. The expected result is approximately: 0D=00 70=D8 75=80
76=E2.
- Now that the PCI Bus Parking code has stabilized,
I've included a normal set of patch settings for the VT8235.
- New code will set the CMD timing of the RAM to 2T on original Pro266 and
KT266 chipsets.
- The full Aureal patch has been restored. The Aureal device will get
Rx40=FF, and the AGP controller will get Rx41=XXX1XXXX.
- CreativeBoost is no longer set to a high value. Previous builds were
raising CreativeBoost (latency of SBLive/Audigy card) to solve crackling
problems, but the system was sometimes less stable as a result. Ensoniq cards,
including Creative PCI128 and CT5880, are still boosted.
Version 0.20 beta 19
- Fixed a bug that was preventing the A7V333 patch (F1=XX0XXXXX) and the
KT266's MWQ patch (95=000XXXXX) from being applied. To prevent future bugs of
this kind, I've cleaned up the code so that it will survive being compiled at
the compiler's highest warning detection level.
Version 0.20 beta 18
- For chipsets that support PCI Bus Parking, the code has been trimmed so it
will write one DWORD-sized register at Rx74 (i.e. registers 74, 75, 76, 77),
period. If KT400 chipsets still freeze up, then something truly strange is
going on.
- The settings for KT266-KT333 has been tweaked. I needed to disable PCI
Delay Transaction for Silicon Image Sil0680 IDE controllers, but when I do so,
Audigy sound cards will start hissing on my Abit KR7A (KT266A) motherboard.
Version 0.20 beta 17
- One bug fix... A typo in the support for PCI Bus Parking was changing too
few settings. No other changes.
Version 0.20 beta 16
- The support for PCI Bus Parking was changing too many settings. Also, a
problem with the code that sets the latency of all sound and IDE/SCSI/RAID
devices has been fixed. This version also has a different layout of code and
data sections in its .SYS file, which may solve strange problems when loading
the driver on Windows XP.
Version 0.20 beta 15
- This build contains a milder KT133A patch than before. It also has the
first support for PCI Bus Parking, which is a feature of the VT8235
SouthBridge chip found in the KT400 and P4X400 chipsets as well as a few KT333
chipsets. A bug preventing the patch from running on Windows 98 has
been fixed.
Version 0.20 beta 14
- This build is being privately released to beta testers first. It contains
an aggressive collection of patch settings for the KT133A chipset. The
equivalent WPCREDIT settings are, approximately: 0D=02 70=C8 75=A0 76=E2. It
also modifies register 0D in all sound and IDE/RAID/SCSI controllers. This is
also the first release of the patch that uses a self-installing EXE file.
Version 0.20 beta 12
- This build is being privately released to beta testers first. It contains
an aggressive collection of patch settings for the KT133A chipset. The
equivalent WPCREDIT settings are, approximately: 0D=02 70=C8 75=A0 76=E2. It
also modifies register 0D in all sound and IDE/RAID/SCSI controllers. This
patch worked well on one A7V133 (KT133A) motherboard when Athlon CPU cooling
was enabled in the BIOS, but it should also work well when cooling is
disabled.
Version 0.20 beta 11
- I had to find yet another KT133A fix for Creative cards because their
Audigy card will crash or reboot the PC if the northbridge's Guaranteed CPU
Time ("latency") is set to zero on an Asus A7V133. This fix involved enabling
PCI Delay Transaction on older Athlon chipsets, which was supposed to harm
USB. Sorry if you have new USB problems after installing this patch. The magic
WPCREDIT formula for this version of the fix is: 0D=02 70=CA 75=83 76=D2.
Version 0.20 beta 10
- I found an alternate fix for SBLive and Ensoniq sound issues on A7V133 and
A7V333 boards. This fix does not enable PCI Master Read Caching. Instead, the
KT133A must be set for zero latency, and the sound card must be set for very
high latency.
- PCI Delay Transaction disabled on all chipsets again.
- Patch for bad BIOSes: Always grant sound cards a little latency.
- Re-added the FRAME-based timer on newer chipsets. When all other settings
are good, this shouldn't be a problem.
Version 0.20 beta 9
- Disable PCI Delay Transaction on non-VLINK chipsets (Comment from user "Chewie":
needed for USB stability on Apollo Pro133A.)
- STPGNT CPU Idle is enabled on Athlon chipsets unless a reason is found to
disable it. This is done to test a feature that will be user-selectable
(default = Do Not Automatically Enable) when I finish this patch. DONE IN THIS
BUILD ONLY. LATER BETAS WILL NOT HAVE THIS UNLESS SPECIFIED.
Version 0.20 beta 8
- Enable PCI Delay Transaction on chipsets
- Remove the enabling of a FRAME-based timer on newer chipsets
Version 0.20 beta 7
- Enable PCI Master Read Caching on older Athlon chipsets, even if STPGNT
Idle is disabled. Software such as CPUCool might enable STPGNT Idle later, and
then PCI Master Read Caching will become necessary.
- Include KX133 chipset in Athlon-specific patches (thanks to Udo Pohl for
the reminder)
Version 0.20 beta 6
- Fixes a bug where an Athlon chipset's STPGNT CPU Idle was not being
disabled when needed
- The broken PCI timer option (Rx73) has been temporarily removed
- STPGNT CPU Idle is enabled on Athlon chipsets unless a reason is found to
disable it. This is done to test a feature that will be user-selectable
(default = Do Not Automatically Enable) when I finish this patch. DONE IN THIS
BUILD ONLY. LATER BETAS WILL NOT HAVE THIS UNLESS SPECIFIED.
- Early support for KT400 (STPGNT Idle only)
Version 0.20 beta 5 no longer sets high latency for IDE/RAID/SCSI
controllers. It also corrects the value of the round-robin policy in register
Rx76 to 01 for new chipsets.
Version 0.20 beta 4 sets registers 0D, 55, 70, 75, and 76 differently for old
chipsets than for new ones. It also disables PCI Master Broken Timer, sets high
latency for all IDE/RAID/SCSI controllers, and some previous patch items were
removed.
Version 0.20 beta 3 fixes a bug, only found in previous 0.20 betas, that
would clear bits 6 and 7 of register Rx75. This version also has the PCI Master
Read Caching re-enabled, but only for KT133/KM133/KLE133 chipsets.
Version 0.20 beta 2 disabled PCI Delay Transaction, which was missing from
the first beta. It also forces the MWQ register to 100 to hopefully fix video
corruption on KLE133 chipsets. And, it disables PCI Master Read Caching, and
sets the Guaranteed CPU Time (0D) register to 02 instead of 00. But, please note
that you can't
read register 0D directly in PCI tools such as WPCREDIT, because the bottom bits are designed to always read
000.